1. Field of the Invention
The present invention is related to noise avoidance in logic design and more particularly to reducing noise in integrated circuit logic chip designs.
2. Background Description
Noise problems caused by cross coupling effects (crosstalk) from runs of parallel integrated circuit wires are well known in the art, especially for application specific integrated circuits (ASICs) designed in technologies based at 0.18 micrometers (microns) and below. Crosstalk can result in incorrect logic responses and, in the extreme, chip failure. Accordingly, to identify potential crosstalk, circuit analysis tools such as GateScope™ from Moscape, Inc. have been developed.
However, typically, these state of the art crosstalk analysis programs identify crosstalk errors only after circuit cell placement and wiring has been completed. At this point in the design, once crosstalk problems are identified, correcting crosstalk problems may require significant effort, e.g., re-placing cells and rewiring circuits or re-buffering individual cells and perhaps even redesigning the logic to split affected nodes. Accordingly, these prior approaches are time consuming and still may not lead to an acceptable chip design in a reasonable period of time.
Thus, there is a need for identifying potential crosstalk in integrated circuit designs.